1. Field of the Invention
The present invention relates to a semiconductor device in which data is stored by charging capacitors, and to an electronic device including the semiconductor device.
2. Description of the Related Art
A DRAM is a memory that requires periodic refreshing, and used for the memory of cellular phones, for example. FIG. 8 is a circuit block diagram showing a part of a conventional DRAM. The configuration and operation of the conventional DRAM is described below briefly using FIG. 8.
A DRAM comprises a memory cell array 5000, sense amplifiers 6000, and read/write circuits 7000. The memory cell array 5000 comprises a plurality of memory cells MC arranged in a row-and-column configuration, a plurality of word lines WL, and a plurality of pairs of bit lines (BL and XBL). In this figure, memory cells MC1 to MC6, word lines WL1 to WL3, and bit lines (BL1 and XBL1) and (BL2 and XBL2) are shown. Each memory cell MC comprises an n-type access transistor nATr and a capacitor C for storing data. Each pair of bit lines (BL and XBL) are connected to the corresponding sense amplifier 6000 and read/write circuit 7000.
The operation of the conventional DRAM is described taking the case of the memory cell MC2. First, the data write operation is described. The word line WL1 is brought to a positive potential to turn on an access transistor nATr2. The bit line BL2 is then brought to a predetermined potential. The predetermined potential is a power supply potential Vcc applied when data xe2x80x9cHxe2x80x9d is written to the capacitor C2, or a ground potential GND applied when data xe2x80x9cLxe2x80x9d is written to the capacitor C2. Data xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d is stored in the capacitor C2 in this manner. The potential of the word line WL1 is then brought to the ground potential GND, whereby the data on the capacitor C2 is preserved.
Next, the data read operation is described. The bit lines BL2 and XBL2 are respectively brought to half the power supply potential (xc2xd) Vcc (precharging of the bit lines BL2 and XBL2). The bit lines BL2 and XBL2 are then separated from the power supply and floated. The word line WL1 is thereafter brought to a positive potential to turn on the access transistor nATr2. Consequently, the potential of the bit line BL2 slightly rises (as much as xcex1) from (xc2xd) Vcc when data xe2x80x9cHxe2x80x9d has been written to the capacitor C2. On the other hand, the potential lowers slightly (as much as xcex1) from (xc2xd) Vcc when data xe2x80x9cLxe2x80x9d has been written to the capacitor C2.
The potential of the bit line XBL2, (xc2xd) Vcc, and that of the bit line BL2 are compared and amplified by the sense amplifier 6000. When the data of the capacitor C2 is xe2x80x9cHxe2x80x9d, the potential of the bit line BL2 becomes Vcc and that of the bit line XBL2 becomes GND. When the data of the capacitor C2 is xe2x80x9cLxe2x80x9d, on the other hand, the potential of the bit line BL2 becomes GND and that of the bit line XBL2 becomes Vcc. Here data reading from the memory cell MC2 is completed. Although the data stored on the capacitor C2 is destroyed by reading, the data is rewritten to the capacitor C2 with the potential of the bit line BL2 when the data has been read.
In a DRAM, when data xe2x80x9cHxe2x80x9d is stored in the capacitors, the data xe2x80x9cHxe2x80x9d changed to data xe2x80x9cLxe2x80x9d even while power is on if left as is. To prevent this, a DRAM requires refreshing. The refreshing period should be as long as possible in order to reduce the power consumption of a DRAM.
The change from data xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d described above is accelerated by various causes. This is described using FIG. 9. FIG. 9 is a circuit diagram of part of a conventional DRAM, showing the same configuration as in FIG. 8. It is assumed that data xe2x80x9cLxe2x80x9d is stored in the capacitor C2 of the memory cell MC2 and data xe2x80x9cHxe2x80x9d in the capacitor C6 of the memory cell MC6. When data is read from the memory cell MC2, the word line WL1 is at a positive potential, the word lines WL2 and WL3 are at the ground potential GND, the bit line BL2 goes to the ground potential GND, and the bit line XBL2 goes to the power supply potential Vcc. In this case, a very small amount of electric charge Q flows from the capacitor C6 of the memory cell MC6 as shown by the arrow (this is referred to as a subthreshold leak current of transistor), and hence the decay from data xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d in the capacitor C6 is accelerated.
An object of the present invention is to provide a semiconductor device of which the power consumption can be reduced and an electronic device using the semiconductor device.
(1) The present invention provides a semiconductor device having a memory cell array comprising a plurality of memory cells and a plurality of word lines and in which the selection and non-selection of the memory cells is controlled by changing a potential of the word lines, wherein:
each of the memory cells comprises an n-type access transistor and a capacitor having a cell plate;
predetermined potential is applied to the cell plate,
a potential of the cell plate during a period when the memory cells are selected is a first potential;
a potential of the cell plate during a period when the memory cells are non-selected is a second potential larger than the first potential; and
a switching of the potential of the cell plates is controlled by changing a potential of the word lines.
In the present invention, the potential of the cell plates during a non-selected period of the memory cells (second potential) is greater than that of the cell plates during a selected period of the memory cells (first potential). By this configuration, the potential of the nodes (drains) of the n-type access transistors connected to the capacitors is raised because of capacitance coupling by the capacitors during a non-selected period. The rise in the potential of the nodes makes it possible to increase the margin of data xe2x80x9cHxe2x80x9d decision level in the capacitors. According to the present invention, the refreshing period therefore can be extended and, consequently, the power consumption can be reduced.
(2) In the present invention,
the semiconductor device may have a plurality of memory cell groups each of which includes a plurality of the memory cells;
the n-type access transistor included in one of the memory cell groups may be controlled by one of the word lines;
the cell plates at the n-type access transistors included in each of the memory cell groups may be connected together; and
the cell plates of one of the memory cell groups may be separated from the other cell plates in a rest of the memory cell groups.
(3) In the present invention, a potential of the cell plate may be switched for each of the memory cell groups.
In this configuration, the potential switching speed of the cell plates can be increased in comparison with the case in which all capacitors of the entire memory cell array are connected together. Moreover, since the capacitance of the cell plates in which the potential is changed is decreased in this embodiment, the power consumption of the semiconductor device can be reduced.
(4) In the present invention, the semiconductor device may have a cell-plate-potential-switching circuit that includes the word lines, a plurality of n-type switch transistors and a plurality of p-type switch transistors, and
in one of the word lines, and one of the n-type switch transistors and one of the p-type switch transistors provided to the one of the word lines,
the one word line may be connected to a gate electrode of the one n-type switch transistor and a gate electrode of the one p-type switch transistor;
one of sources/drains of the one n-type switch transistor may be connected to the cell plate provided to one of the memory cell groups corresponding to the one word line;
the first potential may be applied to another one of the sources/drains of the ore n-type switch transistor;
one of sources/drains of the one p-type switch transistor may be connected to the cell plate provided to one of the memory cell groups corresponding to the one word line; and
the second potential may be applied to another one of the sources/drains of the one p-type witch transistor.
In this configuration, the cell-plate-potential-switching circuit has a simple structure.
(5) In the present invention,
the semiconductor device may have a sense amplifier for amplifying data from the capacitor;
a time at which the cell plate is switched from the second potential to the first potential may be delayed until after a time at which the word lines start selection of the memory cells; and
wherein the sense amplifier may latch the data from the capacitor before a time at which the cell plate is switched to the fist potential.
According to this configuration, reading error when the data in the capacitors is xe2x80x9cHxe2x80x9d can be prevented. The reason will be described in the section of xe2x80x9cmajor effects of semiconductor devicexe2x80x9d in the detailed description of the preferred embodiments.
(6) In the present invention,
the semiconductor device may have a word line decoder, and
a current supply capability of the n-type switch transistor may be smaller than a current supply capability of the word line decoder.
According to this configuration, the timing for switching the cell plates from the second potential to the first potential can be delayed until after the time at which memory cells start to select the word lines.
(7) In the present invention, a capacitance of each of the word lines may be smaller than a capacitance of the cell plate of one of the memory cell groups corresponding to each of the word lines.
According to this configuration, the timing for switching the cell plates from the second potential to the first potential can be delayed until after the time at which memory cells start to select the word lines.
(8) In the present invention, the cell plate of all of the memory cells may be connected together.
According to this configuration it is possible to simplify the structure of the memory cells.
(9) In the present invention, write and/or rewrite may be performed when the potential of the cell plate is the first potential during the period when the memory cells is selected.
(10) In the present invention, the first potential may be one half a power supply potential Vcc.
(11) In the present invention, the semiconductor device may comprise at least one of DRAM (Dynamic RAM), PSRAM (Pseudo static RAM), and VSRAM (Virtually Static RAM).
(12) The present invention further provides an electronic device using the semiconductor device described above.